xsnmaddmdp

VSX Scalar Negative Multiply-Add Type-M Double-Precision

xsnmaddmdp VRT, VRA, VRB, VRC

Computes the negative of the fused multiply-add of the double-precision floating-point operands, storing the result in the target scalar VSX register (Type-M: target register is used as the addend).

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1352

21:31

Format XX3-form

Opcode 0xF0000548

Extension VSX

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
VRC
Source Vector Register

Example

xsnmaddmdp v1, v2, v3, v4

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a VSX scalar fused negative multiply-add operation on double-precision floating-point values using the Type-M form, where VRT is used as the addend operand. Computes -(VRA × VRB + VRT) and stores the result in VRT. The instruction operates on scalar elements (bits 0:63 of the VSX registers) and updates FPSCR exception flags accordingly.

Operation

VRT[0:63] ← -(VRA[0:63] × VRB[0:63] + VRT[0:63])
Update FPSCR exception flags based on floating-point result

Programming Note

Use xsnmaddmdp for performing a fused multiply-add operation on double-precision floating-point numbers, negating the result. Ensure that the target register provides the addend, and be aware that this instruction operates as a single fused step without intermediate rounding.