xvcmpgtdp

VSX Vector Compare Greater Than Double-Precision

xvcmpgtdp XT,XA,XB
xvcmpgtdp. XT,XA,XB

Compares two double-precision floating-point values and sets the target vector register based on the comparison.

Details

For xvcmpgtdp, each element of the source vectors VSR[XA] and VSR[XB] is compared. The result is stored in VSR[XT]. If Rc=1, CR Field 6 is updated with the results of the comparison.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ← 0b0
all_false ← 0b1
all_true ← 0b1
do i = 0 to 1
    reset_xflags()
    src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if src1.class.SNaN | src2.class.SNaN then do
        vxsnan_flag ← 0b1
        if FPSCR.VE=0 then vxvc_flag ← 0b1
    end else vxvc_flag ← IsQNaN(src1) | IsQNaN(src2)
    if src1 > src2 then do
        vresult.dword[i] ← 0xFFFF_FFFF_FFFF_FFFF
        all_false ← 0b0
    end else do
        all_true ← 0b0
        vresult.dword[i] ← 0x0000_0000_0000_0000
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ← ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ← vresult
if Rc=1 then do
    if vex_flag=0 then CR.field[6] ← all_true || 0b0 || all_false || 0b0 else CR.field[6] ← 0bUUUU
end

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.

Example

xvcmpgtdp vs1, vs2, vs3

Encoding

Binary Layout

Format XX3-form

Opcode 0xF000006B

Extension VSX

Registers Altered CR, FPSCR

Operands

XT
Target
XA
Src A
XB
Src B