icbi

Instruction Cache Block Invalidate

icbi RA, RB

Invalidates the instruction cache block associated with the address. Critical for self-modifying code or JITs.

Encoding

Binary Layout

31

0:5

/

6:10

RA

11:15

RB

16:20

982

21:30

/

31

 

Format X-form

Opcode 0x7C0007AC

Extension Base

Operands

• RA
  Base Address
• RB
  Index Address

Example

icbi 0, r3

// Invalidate instruction cache at r3.

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Invalidates the instruction cache block that contains the address RA + RB, forcing subsequent instruction fetches from that block to reload from lower cache levels or memory. Essential for self-modifying code and JIT compilers. May affect performance on some implementations.

Operation

EA ← (RA) + (RB)
Invalidate_ICacheBlock(EA)

Programming Note

Use icbi to ensure that changes to executable code in memory are reflected in the instruction cache. This is crucial after modifying code at runtime. Ensure the address is properly aligned; typically, block boundaries align with cache line sizes. This instruction operates at user privilege level and may raise an exception if the address is invalid or access is denied.