icbt

Instruction Cache Block Touch

icbt RA, RB

Provides a hint that the program will soon execute code from the block containing the byte addressed by EA, and that the block should be loaded into the cache specified by the CT field.

Encoding

Binary Layout

31

0:5

/

6:10

RA

11:15

RB

16:20

22

21:30

/

31

 

Format X-form

Opcode 0x7C00002C

Extension Base

Operands

• RA
  Base
• RB
  Index
• CT
  Cache Type Field

Example

icbt r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Issues a hint that the program will soon execute code from a block and requests that the block be preloaded into the instruction cache. The effective address is computed from RA + RB, and an optional cache-type field (CT, encoded in bits 21-25 of the instruction) specifies which cache level. This is a hint only and does not guarantee a load; no registers are modified.

Operation

EA ← (RA) + (RB)
// Hint to instruction cache that block at EA should be preloaded
// CT field (from instruction bits 21-25) specifies cache type
// No register modification

Programming Note

The hint is ignored if the block is Caching Inhibited. This instruction treated as a Load (see Section 4.3), except that the system data storage error handler is not invoked, and reference and change recording need not be done.