vnegw

Vector Negate Word

vnegw vD, vB

Negates the contents of each word element in a vector register.

Details

For vnegw, the one's-complement of each signed integer in word elements of VSR[VRB+32] is added to 1 and placed into corresponding word elements of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(¬src + 1)
end

Programming Note

The vnegw instruction negates each signed integer in the word elements of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so input data must be properly aligned. Be cautious of overflow conditions when negating large positive numbers.

Example

vnegw vd, vb

Encoding

Binary Layout
000100
0
vD
6
00110
11
vB
16
11000
21
000010
 
Format VX-form
Opcode 0x10000604
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vB
    Source
  • VRT
    Target Vector Register
  • VRB
    Source Vector Register
  • VX
    Destination Vector Register
  • VS
    Source Vector Register