vnegw

Vector Negate Word

vnegw vD, vB

Negates the contents of each word element in a vector register.

Encoding

Binary Layout

000100

0:5

vD

6:10

00110

11:15

vB

16:20

11000

21:25

000010

26:31

 

Format VX-form

Opcode 0x10060602

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register
• VX
  Destination Vector Register
• VS
  Source Vector Register

Example

vnegw vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vnegw, the one's-complement of each signed integer in word elements of VSR[VRB+32] is added to 1 and placed into corresponding word elements of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(¬src + 1)
end

Programming Note

The vnegw instruction negates each signed integer in the word elements of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so input data must be properly aligned. Be cautious of overflow conditions when negating large positive numbers.