xvcvdpsxds

VSX Vector Convert Double-Precision to Signed Doubleword for- mat XX2-form

xvcvdpsxds XT, XB

Converts a double-precision floating-point value to a signed doubleword integer, rounding according to the current rounding mode.

Details

The xvcvdpsxds instruction converts a double-precision floating-point value in VSR[XB] to a signed doubleword integer and stores the result in VSR[XT]. The conversion follows the IEEE 754 standard for rounding modes. If the source value is outside the range of representable signed doublewords, an exception may be raised.

Pseudocode Operation

for i = 0 to 1 do
    src <- VSR[XB][i]
    if src is a NaN then
        T(Nmin), fx(VXCVI)
        if src is a SNaN then
            fx(VXSNAN)
        endif
    else if src ≤ Nmin-1 then
        T(Nmin), fx(VXCVI)
    else if Nmin-1 < src < Nmin then
        if FPSCR.XE = 0 then
            T(Nmin), fx(XX)
        else
            fx(XX), error()
        endif
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        if FPSCR.XE = 0 then
            T(f2i(trunc(src))), fx(XX)
        else
            fx(XX), error()
        endif
    else if src = Nmax then
        Note: This case cannot occur as Nmax is not representable in DP format but is included here for completeness.
    else if Nmax < src < Nmax+1 then
        if FPSCR.XE = 0 then
            T(Nmax), fx(XX)
        else
            fx(XX), error()
        endif
    else if src ≥ Nmax+1 then
        T(Nmin), fx(VXCVI)
    endif
endfor

Programming Note

xvcvdpsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode.

Example

xvcvdpsxds vs1, vs3

Encoding

Binary Layout
60
0
XT
6
/
11
XB
16
472
21
 
Format XX2-form
Opcode 0xF00001D8
Extension VSX
Registers Altered FPSCR, VSR[XT], VSR[XB]

Operands

  • XT
    Target
  • XB
    Source