xvcvdpsxds

VSX Vector Convert Double-Precision to Signed Doubleword for- mat XX2-form

xvcvdpsxds XT, XB

Converts a double-precision floating-point value to a signed doubleword integer, rounding according to the current rounding mode.

Encoding

Binary Layout

60

0:5

XT

6:10

/

11:15

XB

16:20

472

21:31

 

Format XX2-form

Opcode 0xF0000760

Extension VSX

Operands

• XT
  Target
• XB
  Source

Example

xvcvdpsxds vs1, vs3

Registers Altered

FPSCR, VSR[XT], VSR[XB]

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts two double-precision floating-point values in VSR[XB] to signed 64-bit integer format (doubleword) and places the results in VSR[XT]. Rounding is performed according to the current rounding mode in FPSCR. On overflow or invalid operation, the result is saturated to the maximum or minimum signed 64-bit integer.

Operation

VSR[XT].element[0] ← ConvertDP_to_SXD_Round(VSR[XB].element[0], RoundMode)
VSR[XT].element[1] ← ConvertDP_to_SXD_Round(VSR[XB].element[1], RoundMode)

Programming Note

xvcvdpsxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode.