lxssp

Load VSX Scalar Single-Precision

lxssp RT,RA,RB

Accesses a floating-point operand in single-precision format from storage, converts it to double-precision format, and loads it into a VSR.

Encoding

Binary Layout

VRT

Format XX2-form

Opcode 0xE4000003

Extension VSX

Operands

RT
Target Vector-Specific Register
RA
Base Address General Purpose Register
RB
Offset General Purpose Register
VRT
Target VSX Register
disp
Displacement

Example

lxssp r3, r4, r5

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

When Big-Endian byte ordering is employed, the contents of the word in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 0 of load_data, the contents of the byte in storage at address EA+1 are placed into byte 1 of load_data, the contents of the byte in storage at address EA+2 are placed into byte 2 of load_data, and the contents of the byte in storage at address EA+3 are placed into byte 3 of load_data. When Little-Endian byte ordering is employed, the contents of the word in storage at address EA are placed into load_data in such an order that; the contents of the byte in storage at address EA are placed into byte 3 of load_data, the contents of the byte in storage at address EA+1 are placed into byte 2 of load_data, the contents of the byte in storage at address EA+2 are placed into byte 1 of load_data, and the contents of the byte in storage at address EA+3 are placed into byte 0 of load_data. The contents of doubleword element 1 of VSR[VRT+32] are set to 0.

Operation

if MSR.VEC=0 then Vector_Unavailable()
EA ← (RA|0) + EXTS64(DS||0b00)
load_data ← MEM(EA,4)
result ← bfp_CONVERT_FROM_BFP32(MEM(EA,4))
VSR[VRT+32].dword[0] ← bfp64_CONVERT_FROM_BFP(result)
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

Programming Note

The lxssp instruction loads a single-precision floating-point value from memory into the VSX register, ensuring proper byte ordering based on the system's endianness. It is commonly used for loading scalar floating-point data into VSX registers for further processing. Ensure that the address (EA) is properly aligned to avoid potential performance penalties or exceptions. This instruction operates at user privilege level and will raise a Vector_Unavailable exception if the VEC bit in the MSR register is not set.