xssqrtqp

VSX Scalar Square Root Quad-Precision

xssqrtqp vD, vB

Computes the square root of a quad-precision floating-point value with unbounded significand precision and exponent range.

Encoding

Binary Layout

0:5

FRT

6:10

11:15

FRB

16:20

674

21:30

Format X-form

Opcode 0xFC1B0648

Extension VSX

Operands

vD
Target
vB
Source
VRT
Target Vector-Specific Register
VRB
Source Vector-Specific Register
VRA
Target Vector-Specific Register

Example

xssqrtqp vd, vb

Registers Altered

FPSCR, VSR[VRT+32]

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The normalized square root of src is produced with unbounded significand precision and exponent range. If RO=1, the rounding mode is Round to Odd; otherwise, it is specified by RN.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_SQUARE_ROOT(src)
rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxsqrt_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[VRT+32] ← result
  FPSCR.FPRF ← fprf_CLASS_BFP128(result)
end
FPSCR.FR ← (vx_flag=0) & inc_flag
FPSCR.FI ← (vx_flag=0) & xx_flag

Programming Note

The xssqrtqp instruction computes the square root of a quad-precision floating-point number. Ensure that VSX is enabled in the MSR register to avoid exceptions. Be cautious with rounding modes; setting RO=1 enables Round to Odd, which may differ from standard rounding behaviors. This instruction handles special cases like NaNs and infinities, updating the FPSCR accordingly.