xsnmaddqpo

VSX Scalar Negative Multiply-Add Quad-Precision (Overflow)

xsnmaddqpo VRT,VRA,VRB

Performs a negative multiply-add operation on quad-precision floating-point values.

Encoding

Binary Layout

11110001

0:5

00000000

6:10

00000000

11:15

1000

16:31

 

Format X-form

Opcode 0xFC000388

Extension VSX

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

xsnmaddqp v1, v2, v3

Registers Altered

FPSCR FPRF FR FI FX VXSNAN VXIMZ VXISI OX UX XX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a scalar negative multiply-add operation on quad-precision floating-point values, computing VRT = -(VRA × VRB) + VRT. The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.

Operation

VRT[0:127] ← -(VRA[0:127] × VRB[0:127]) + VRT[0:127]
FPSCR ← update_exception_flags(FPSCR, result)

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction

Programming Note

This instruction is used for performing a scalar negative multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the OX and UX flags in the FPSCR register. The result is rounded according to the rounding mode specified in FPSCR.RN.