xsrdpi

Round to Floating-Point Integer (Double-Precision)

xsrdpi VRT, VRA

Rounds a double-precision floating-point value to an integer using the specified rounding mode.

Encoding

Binary Layout

60

0:5

T

6:8

B

9:10

11

11:15

16

16:20

BX

21:30

TX

31

 

Format X-form

Opcode 0xF0000124

Extension VSX

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• XT
  Target Vector-Scalar Register
• XB
  Source Vector-Scalar Register

Example

xsrdpi v1, v2

Registers Altered

FPSCR (FPRF, FX, VXSNAN, FR, FI)

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The result is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b100, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0

Programming Note

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.