vprtybd

Vector Parity Byte Doubleword

vprtybd vD, vB

Computes parity of bytes within doublewords.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1604

21:31

Format VX-form

Opcode 0x10090602

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source

Example

vprtybd vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Computes the parity (XOR of all bits) of each byte within the 2 doubleword elements of vB and stores a single parity bit (0 or 1) into the corresponding byte position of vD, with each doubleword's 8 bytes reduced to their individual parities. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

Operation

for i in 0 to 1 do
  for j in 0 to 7 do
    byte_index ← i*8 + j
    byte_val ← vB[byte_index*8 : byte_index*8+7]
    parity ← XOR(byte_val[0], byte_val[1], ..., byte_val[7])
    vD[byte_index*8 : byte_index*8+7] ← (0x00) || parity

Programming Note

This instruction is useful for calculating the parity of the least significant bit in each byte of a doubleword element. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation is performed on 64-bit elements, and the result is stored in the corresponding output vector register. There are no specific alignment requirements for the input data.