vpkuwum

Vector Pack Unsigned Word Unsigned Modulo

vpkuwum vD, vA, vB

Packs the upper half of each word from two vector registers into a single vector register using modulo arithmetic.

Details

The instruction concatenates the contents of VSR[VRA+32] and VSR[VRB+32], then extracts the upper half of each word (bits 16:31) and places them into the corresponding halfword elements of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
do i = 0 to 7
    VSR[VRT+32].hword[i] ← vsrc.word[i].bit[16:31]
end

Programming Note

This instruction is used for packing the upper half of each word from two vector registers into a single destination register. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector Unavailable exception will be raised. The operation requires both source vectors to be aligned on 16-byte boundaries for optimal performance.

Example

vpkuwum vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
78
 
Format VX-form
Opcode 0x1000004E
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register