pmxvf64gernn

Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate

pmxvf64gernn AT,XAp,XB,XMSK,YMSK

Performs a prefixed masked VSX vector 64-bit floating-point GER (rank-1 update) with negative multiply and negative accumulate.

Encoding

Binary Layout

000001

0:5

11100

6:10

1

11

Rc

12

//

13

///..

14

?

15:63

 

Format MMIRR:XX3-form

Opcode 0x07900000EC0007D0

Extension MMA

Operands

• AT
  Target accumulator. ACC[AT] holds a 4x2 matrix of double-precision values.
• XAp
  Source VSR pair (even/odd). VSR[XAp] and VSR[XAp+1] are concatenated to supply the four row values.
• XB
  Source VSR supplying the two column values.
• XMSK
  4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero.
• YMSK
  2-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero.

Example

pmxvf64gernn

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

A prefixed MMA instruction that performs a masked 64-bit floating-point GER (generalized matrix element rank-1 update) with negative multiply and negative accumulate into an accumulator. The operation updates a 4×4 matrix accumulator using VSX registers with optional row and column masking. This instruction requires MMA support and updates FPSCR.

Operation

vsrcX ← VSR[XAp] || VSR[XAp+1]
vsrcY ← VSR[XB]
do i = 0 to 3
  do j = 0 to 1
    if XMSK.bit[i]=1 & YMSK.bit[j]=1 then
      ACC[AT][i].dword[j] ← -( vsrcX.dword[i] × vsrcY.dword[j] + ACC[AT][i].dword[j] )
    else
      ACC[AT][i].dword[j] ← 0

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.