pmxvf64gernn

Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate

pmxvf64gernn

Performs a prefixed masked VSX vector 64-bit floating-point GER (rank-1 update) with negative multiply and negative accumulate.

Details

A prefixed MMA instruction that performs a masked 64-bit floating-point GER (generalized matrix element rank-1 update) with negative multiply and negative accumulate into an accumulator. The operation updates a 4×4 matrix accumulator using VSX registers with optional row and column masking. This instruction requires MMA support and updates FPSCR.

Pseudocode Operation

ACC ← -1.0 * (RA64 × RB64) + (-1.0) * ACC

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

pmxvf64gernn

Encoding

Binary Layout
000001
0
11100
6
1
11
Rc
12
//
13
///..
14
?
15
 
Format MMIRR:XX3-form
Opcode 0x3F800000
Extension MMA

Operands

  • ACC
    4×4 matrix accumulator (4 consecutive even VSRs) that is updated with the negated product and negated accumulate result.
  • RA
    Source VSX vector register containing 64-bit floating-point values for row operand.
  • RB
    Source VSX vector register containing 64-bit floating-point values for column operand.
  • RMask
    Optional 3-bit row mask controlling which rows participate in the update.
  • CMask
    Optional 3-bit column mask controlling which columns participate in the update.