vupklsb

Vector Unpack Low Signed Byte

vupklsb vD, vB

Unpacks low 8 signed bytes to 8 signed halfwords.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

654

21:31

Format VX-form

Opcode 0x1000028E

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source

Example

vupklsb vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Unpacks the eight low-order (rightmost) signed bytes from vB into eight signed halfwords in vD, sign-extending each byte to 16 bits. This is a VMX instruction that does not modify condition or status registers.

Operation

vD[0:15] ← sign_extend(vB[120:127])
vD[16:31] ← sign_extend(vB[112:119])
vD[32:47] ← sign_extend(vB[104:111])
vD[48:63] ← sign_extend(vB[96:103])
vD[64:79] ← sign_extend(vB[88:95])
vD[80:95] ← sign_extend(vB[80:87])
vD[96:111] ← sign_extend(vB[72:79])
vD[112:127] ← sign_extend(vB[64:71])

Programming Note

This instruction is useful for processing byte data by converting it into signed halfwords, which can be beneficial for operations requiring sign extension. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will occur. The input vector must be properly aligned to avoid unexpected results.