xsrsp

VSX Scalar Round to Single-Precision

xsrsp XT,XB

Rounds a double-precision floating-point value in VSR[XB] to single-precision and stores the result in VSR[XT].

Details

The instruction rounds the double-precision floating-point value in doubleword element 0 of VSR[XB] to single-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, and doubleword element 1 of VSR[XT] is set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, src)
result32 ← bfp32_CONVERT_FROM_BFP(rnd)
result64 ← bfp64_CONVERT_FROM_BFP(rnd)

if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vex_flag ← FPSCR.VE & vxsnan_flag

if vex_flag=0 then do
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP32(result32)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xsrsp vs1, vs3

Encoding

Binary Layout
18
0
T
6
B
11
BX
16
TX
21
 
Format X-form
Opcode 0xF0000464
Extension VSX
Registers Altered FPSCR, VSR[32×TX+T].dword[0], VSR[32×TX+T].dword[1]

Operands

  • XT
    Target Vector-Scalar Register
  • XB
    Source Vector-Scalar Register