vrlqnm

Vector Rotate Left Quadword then AND with Mask VX-form

vrlqnm VRT,VRA,VRB

Rotates the contents of a vector register left by a specified number of bits and performs a bitwise AND operation with a mask derived from another vector register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:31

Format VX-form

Opcode 0x10000145

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vrlqnm v1, v2, v3

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rotates the quadword element in VRA left by a number of bits specified in VRB, then performs a bitwise AND with a mask derived from the lower bits of VRB to produce the result in VRT. No condition flags are affected.

Operation

shamt ← (VRB[120:127]) & 0x7F
mask_bits ← (VRB[120:127]) & 0x3F
rotated ← (VRA << shamt) | (VRA >> (128 - shamt))
mask ← Generate_Mask(mask_bits)
VRT ← rotated & mask

Programming Note

The vrlqnm instruction is used for vectorized operations involving rotation and masking of quadword data. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1, otherwise a Vector_Unavailable exception will be raised. The mask generation from bits 41:47 and 49:55 of VSR[VRB+32] should be carefully managed to achieve the desired bitwise AND operation result.