vextsb2w

Vector Extend Sign Byte To Word

vextsb2w vD, vB

Sign-extends each byte in a vector to a word.

Encoding

Binary Layout

4

0:5

VRT

6:10

16

11:15

VRB

16:20

1538

21:31

 

Format VX-form

Opcode 0x10100602

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vextsb2w vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vextsb2w, the signed integer in bits 24:31 of each word element of VSR[VRB+32] is sign-extended and placed into the corresponding word element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i].bit[24:31]
    VSR[VRT+32].word[i] ← EXTS32(src)
end

Programming Note

This instruction is used to sign-extend the most significant byte of each word in a vector register. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector Unavailable exception will be raised. The operation processes four words per vector register, and it's important to handle exceptions properly to avoid program crashes.