vpmsumh

Vector Polynomial Multiply-Sum Halfword

vpmsumh vD, vA, vB

Performs GF(2) polynomial arithmetic on halfwords.

Encoding

Binary Layout

000100

0:5

6:10

11:15

16:20

10001

21:25

001000

26:31

Format VX-form

Opcode 0x10000448

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vpmsumh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs GF(2) polynomial multiplication on pairs of 16-bit halfword elements from vA and vB, accumulating the results into vD. This VMX/AltiVec instruction is used in cryptographic and polynomial arithmetic operations and does not modify condition registers or exception status.

Operation

for i in 0 to 3:
  prod ← PolyMultiply_GF2(vA[32*i:32*i+31], vB[32*i:32*i+31])
  vD[64*i:64*i+63] ← vD[64*i:64*i+63] XOR prod

Programming Note

The vpmsumh instruction is commonly used for finite field arithmetic operations, particularly in cryptographic algorithms. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of alignment requirements; source vectors must be aligned to halfword boundaries. This instruction operates at a privilege level where vector operations are supported, typically user or supervisor mode. Exception conditions include a Vector Unavailable exception if the facility is not enabled.