vshasigmaw

Vector SHA-256 Sigma Word

vshasigmaw vD, vA, ST, SIX

Performs the Sigma0/Sigma1/sigma0/sigma1 functions for SHA-256.

Details

Performs one of the four SHA-256 sigma functions (Sigma0, Sigma1, sigma0, or sigma1) on each 32-bit word in the source vector and stores the result in the destination vector. The ST field selects between Sigma-type and sigma-type operations, and SIX selects the specific operation. This is a Vector Crypto instruction that operates on four 32-bit elements in parallel within a 128-bit vector register. No condition or status registers are affected.

Pseudocode Operation

for i = 0 to 3: vD[32i:32i+31] ← SHA256_sigma(vA[32i:32i+31], ST, SIX)

Programming Note

The vshasigmaw instruction is used to perform SHA-256 sigma or sigma-like functions on vector register elements. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. The instruction operates on each 32-bit word of the source vector, applying different bitwise rotations and XORs based on the ST and SIX fields. This instruction requires supervisor privilege level to execute.

Example

vshasigmaw v1, v2, 0, 0

// SHA-256 Acceleration.

Encoding

Binary Layout
4
0
VRT
6
VRA
11
ST
16
SIX
17
 
Format VX-form
Opcode 0x10000682
Extension Vector Crypto
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Source
  • ST
    Sigma Type (0/1)
  • SIX
    Shift Index (Immediate)
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register