xvcvsxwdp

VSX Vector Convert Signed Word to Double-Precision format XX2-form

xvcvsxwdp XT,XB

Converts signed word elements from a vector register to double-precision floating-point elements in another vector register.

Encoding

Binary Layout

18

0:5

T

6:10

B

11:15

BX

16:20

TX

21:31

 

Format XX2-form

Opcode 0xF00003E0

Extension VSX

Operands

• XT
  Target Vector Register
• XB
  Source Vector Register

Example

xvcvsxwdp vs1, vs3

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction converts each signed integer value in bits 0:31 of doubleword element i of VSR[XB] into double-precision format and places it into doubleword element i of VSR[XT].

Operation

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    src ←bfp_CONVERT_FROM_SI32(VSR[32×BX+B].dword[i].word[0])
    VSR[32×TX+T].dword[i] ←bfp64_CONVERT_FROM_BFP(src)
end

Programming Note

This instruction is used to convert signed 32-bit integers in a VSX register to double-precision floating-point format. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction; otherwise, it will raise an exception. The conversion is performed for each of the two doublewords in the source register and stored in the corresponding positions of the target register.