xvnegsp

VSX Vector Negate Single-Precision

xvnegsp XT, XB

Negates the contents of a single-precision floating-point register.

Encoding

Binary Layout
60
0:5
XT
6:10
0
11:15
XB
16:20
425
21:31
 
Format XX2-form
Opcode 0xF00006E4
Extension VSX

Operands

  • XT
    Target
  • XB
    Source
  • VRT
    Target Vector Register
  • VRB
    Source Vector Register

Example

xvnegsp vs1, vs3

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

VSX Vector Negate Single-Precision negates four single-precision floating-point elements from VSX register XB, storing the results in VSX register XT. This VSX category instruction inverts the sign bit of each 32-bit element and does not affect floating-point status flags.

Operation

XT[0:31] ← -XB[0:31]
XT[32:63] ← -XB[32:63]
XT[64:95] ← -XB[64:95]
XT[96:127] ← -XB[96:127]

Programming Note

Use xvnegsp to negate each single-precision float in a VSX vector. Ensure vectors are properly aligned; misalignment can cause exceptions. This instruction operates at user privilege level.