xvrspiz

VSX Vector Round to Single-Precision Integer using round toward Zero

xvrspiz XT,XB

Rounds each single-precision floating-point element of a vector towards zero and stores the result in another vector.

Details

For xvrspiz, each single-precision floating-point operand in word elements of VSR[XB] is rounded to an integer using the rounding mode Round toward Zero. The results are placed into corresponding word elements of VSR[XT]. If a Signalling NaN is encountered, it is converted to a Quiet NaN and VXSNAN is set.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 3
    reset_xflags()

    src ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    rnd ←bfp_ROUND_TO_INTEGER(0b001, src)

    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

This instruction is commonly used for converting single-precision floating-point numbers to integers by truncating towards zero. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register; otherwise, an exception will be raised. Be cautious with Signalling NaNs, as they are converted to Quiet NaNs and VXSNAN is set in the FPSCR register. The instruction processes four elements at a time, so ensure proper alignment of input vectors.

Example

xvrspiz vs1, vs3

Encoding

Binary Layout
111100
0
XT
6
//
11
XB
16
01001
21
1001
 
Format XX2-form
Opcode 0xF0000264
Extension VSX
Registers Altered FPSCR, VXSNAN

Operands

  • XT
    Target Vector-Specific Register
  • XB
    Source Vector-Specific Register
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register