pstfd

Prefixed Store Floating-Point Double MLS:D-form

pstfd FRT,RA,RB

Stores a double-precision floating-point value from a register to memory.

Encoding

Binary Layout

01

0:5

100

6:10

Rc

11

.//..

12

FRT

13:17

RA

18:22

RB

23:63

 

Format MLS:D-form

Opcode 0x06000000D8000000

Extension Prefixed

Operands

• FRT
  Target Floating-Point Register
• RA
  Base General Purpose Register
• RB
  Offset General Purpose Register

Example

pstfd f1, r4, r5

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a double-precision floating-point value from a floating-point register to memory using a prefixed instruction format (64 bits total: 32-bit prefix + 32-bit instruction). The addressing mode uses a base register and a displacement that can be formed from the prefix and suffix portions, allowing for a wider displacement range than non-prefixed forms. This instruction does not update condition registers.

Operation

displacement ← (prefix_immediate || suffix_immediate) [sign-extended to 64 bits]
EA ← RA + displacement
[EA:EA+7] ← FRT[0:63]

Programming Note

The pstfd instruction is used to store a double-precision floating-point value from a register into memory. Ensure that the effective address calculation does not result in an overflow or underflow. This instruction requires the EA to be aligned on an 8-byte boundary for optimal performance and correctness.