Prefixed Instructions
26 PowerISA instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| paddi | paddi RT, RA, SI, R | MLS:D-form | Adds 34-bit immediate. |
| pla | pla RT, label | Pseudo | Pseudo-instruction for paddi with R=1. Loads the address of a label. |
| plbz | plbz RT, D34(RA), R | MLS:D-form | Loads a byte and zero-extends it, using a 34-bit offset. |
| pld | pld RT, D34(RA), R | MLS:D-form | Loads a 64-bit value from memory using a 34-bit immediate offset (PC-relative or absolute). |
| plfd | plfd RT,RA,RB | D-form | Loads a double-precision floating-point value from memory into a VSX register. |
| plh | plh RT, D(RA), R | MLS:D-form | Loads 16-bit halfword using 34-bit offset. |
| plha | plha RT, D(RA), R | MLS:D-form | Loads 16-bit halfword (Sign Extended) using 34-bit offset. |
| pli | pli RT, SI34 | MLS:D-form | Loads a 34-bit signed immediate into a register. (Replaces multiple 'lis/ori' instructions). |
| plq | plq RTp, D(RA), R | MLS:D-form | Loads 128 bits into two GPRs using a 34-bit offset. |
| plwa | plwa RT, D(RA), R | MLS:D-form | Loads 32-bit word (Sign Extended) using 34-bit offset. |
| plwz | plwz RT, D34(RA), R | MLS:D-form | Loads a 32-bit word and zero-extends it to 64 bits, using a 34-bit offset. |
| plxv | plxv RT,RA,RB | D-form | Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement. |
| plxvp | plxvp XT, D(RA), R | 8LS:D-form | Loads a 256-bit vector pair with 34-bit offset. |
| pmxvbf16ger2 | pmxvbf16ger2 AT, XA, XB, XMSK, YMSK | MMIRR-form | Matrix Multiply Assist (MMA) instruction. Computes ACC <- ACC + (A * B) using BF16 inputs. |
| pmxvf64ger | pmxvf64ger AT, XA, XB, XMSK, YMSK | MMIRR-form | Masked version of Double-Precision MMA. |
| pmxvi4ger8 | pmxvi4ger8 AT, XA, XB, XMSK, YMSK | MMIRR-form | Masked 4-bit integer matrix multiply. |
| pmxvi4ger8pp | pmxvi4ger8pp AT, XA, XB, XMSK, YMSK | MMIRR-form | Masked unsigned 4-bit integer matrix multiply. |
| pmxvi8ger4 | pmxvi8ger4 AT, XA, XB, XMSK, YMSK | MMIRR-form | Masked version of 8-bit integer MMA. |
| pnop | pnop | *-form | No operation is performed. |
| pstb | pstb RS, D(RA), R | MLS:D-form | Stores byte using 34-bit offset. |
| pstfd | pstfd FRT,RA,RB | MLS:D-form | Stores a double-precision floating-point value from a register to memory. |
| psth | psth RS, D(RA), R | MLS:D-form | Stores halfword using 34-bit offset. |
| pstq | pstq RSp, D(RA), R | MLS:D-form | Stores 128 bits from two GPRs using a 34-bit offset. |
| pststd | pststd RS, D34(RA), R | MLS:D-form | Stores a 64-bit value to memory using a 34-bit immediate offset. |
| pstw | pstw RS, D(RA), R | MLS:D-form | Stores word using 34-bit offset. |
| pstxvp | pstxvp XS, D(RA), R | 8LS:D-form | Stores a 256-bit vector pair with 34-bit offset. |