pstxvp

Prefixed Store VSX Vector Pair

pstxvp XS, D(RA), R

Stores a 256-bit vector pair with 34-bit offset.

Encoding

Binary Layout

1

0:5

2

6:7

R

8

0

9:13

D0

14:31

62

32:37

XS

38:42

RA

43:47

D1

48:63

 

Format 8LS:D-form

Opcode 0x04000000F8000000

Extension Prefixed

Operands

• XS
  Source
• D
  Offset
• RA
  Base
• R
  PC-Rel

Example

pstxvp vs1, 0(r4), 0

Registers Altered

PC

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a 256-bit (32-byte) vector pair from XS and XS+1 to memory using a 34-bit signed offset encoded as a 8-byte prefix + suffix. When R=0, the offset is relative to RA; when R=1, the offset is relative to the current instruction address. Requires VSX and Prefixed instruction support.

Operation

D ← EXTS(D0 || D1); EA ← (R=0 ? (RA) : NIA) + D; [EA] ← XS; [EA+16] ← (XS+1)

Programming Note

The pstxvp instruction is used to store a VSX vector pair from the VSR registers to memory. It supports both prefixed and non-prefixed addressing modes. Ensure that the destination address is properly aligned for optimal performance. This instruction operates at privilege level 0.