vmulhud

Vector Multiply High Unsigned Doubleword

vmulhud vD, vA, vB

Multiplies unsigned doublewords, returning the high 64 bits.

Details

Multiplies each pair of unsigned 64-bit doublewords from vA and vB, producing 128-bit products, and places the high 64 bits of each product into the corresponding 64-bit doubleword of vD. Two independent doubleword multiplications are performed. No condition register or status field modifications occur.

Pseudocode Operation

for i = 0 to 1 do
  product ← (vA[i*64:(i+1)*64]) × (vB[i*64:(i+1)*64])
  vD[i*64:(i+1)*64] ← product[64:127]
end for

Programming Note

The vmulhud instruction is used for high-precision multiplication of unsigned doublewords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each pair of elements from two source vectors and stores the upper 64 bits of their product in the destination vector. Be cautious with alignment as unaligned access can lead to exceptions.

Example

vmulhud vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
712
21
 
Format VX-form
Opcode 0x100002C9
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B