vmulhud

Vector Multiply High Unsigned Doubleword

vmulhud vD, vA, vB

Multiplies unsigned doublewords, returning the high 64 bits.

Details

The vmulhud instruction multiplies each unsigned doubleword element from two source vectors and stores the high-order 64 bits of the resulting 128-bit product into corresponding elements of a destination vector.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 1
   src1 ←EXTZ(VSR[VRA+32].dword[i])
   src2 ←EXTZ(VSR[VRB+32].dword[i])
   VSR[VRT+32].dword[i] ←CHOP64((src1 × src2) >> 64)
end

Programming Note

The vmulhud instruction is used for high-precision multiplication of unsigned doublewords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each pair of elements from two source vectors and stores the upper 64 bits of their product in the destination vector. Be cautious with alignment as unaligned access can lead to exceptions.

Example

vmulhud vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
712
21
 
Format VX-form
Opcode 0x100002C8
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B