xscvqpswz

VSX Scalar Convert with round to zero Quad-Precision to Signed Word format

xscvqpswz VRT,VRB

Converts a quad-precision floating-point value to a signed word format.

Encoding

Binary Layout

0

0:5

VRT

6:10

VRB

11:15

11

16:20

9

21:25

6

26:30

0

31

 

Format X-form

Opcode 0xFC090688

Extension VSX

Operands

• VRT
  Target Vector-Scalar Register
• VRB
  Source Vector-Scalar Register

Example

xscvqpswz v1, v3

Registers Altered

FPSCR, VXSNAN, VXCVI, XX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts a quad-precision floating-point value from the source VSR to a signed 32-bit word integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Out-of-range values saturate to the limits of signed 32-bit representation; FPSCR is updated.

Operation

VRT[0:31] ← ConvertToSignedWord_RoundTowardZero(VRB[0:127])
VRT[32:127] ← 0

Programming Note

The xscvqpswz instruction converts a quad-precision floating-point value to a signed word, rounding towards zero. It handles NaNs by setting the result to 0xFFFF_FFFF_8000_0000 and flags VXSNAN and VXCVI accordingly. For infinities, it sets the result to the maximum or minimum signed word value based on the sign of the infinity. Ensure that VSX is enabled (MSR.VSX=1) before using this instruction; otherwise, a VSX_Unavailable exception will be raised.