xscvqpswz

VSX Scalar Convert with round to zero Quad-Precision to Signed Word format

xscvqpswz VRT,VRB

Converts a quad-precision floating-point value to a signed word format.

Details

The xscvqpswz instruction converts a quad-precision floating-point value in VSR[VRB+32] to a signed word format and places the result into doubleword element 0 of VSR[VRT+32]. The conversion follows specific rules for handling NaNs, infinities, zeros, and out-of-range values.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
src ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ← 0
vxcvi_flag ← 0
if src.class.QNaN=1 | src.class.SNaN=1 then do
    result ← 0xFFFF_FFFF_8000_0000
    vxsnan_flag ← src.class.SNaN
    vxcvi_flag ← 1
end else if src.class.Infinity=1 then do
    vxcvi_flag ← 1
    if src.sign=0 then
        result ← 0x0000_0000_7FFF_FFFF
    else
        result ← 0xFFFF_FFFF_8000_0000
end else if src.class.Zero=1 then
    result ← 0x0000_0000_0000_0000
else do
    rnd ← bfp_ROUND_TO_INTEGER(0b001,src)
    if bfp_COMPARE_GT(rnd, +231-1) then do
        result ← 0x0000_0000_7FFF_FFFF
        vxcvi_flag ← 1
    end else if bfp_COMPARE_LT(rnd, -231) then do
        result ← 0xFFFF_FFFF_8000_0000
        vxcvi_flag ← 1
    end else do
        result ← si64_CONVERT_FROM_BFP(rnd)
        if xx_flag=1 then SetFX(FPSCR.XX)
    end
end
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxcvi_flag=1 then SetFX(FPSCR.VXCVI)
vx_flag ← vxsnan_flag | vxcvi_flag
VSR[VRT+32].dword[0] ← result
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FPRF ← 0bUUUUU
FPSCR.FR ← 0
FPSCR.FI ← (vx_flag=0) & xx_flag
ex_flag ← FPSCR.VE & vx_flag
if ex_flag=0 then do
    VSR[VRT+32] and FPRF are not modified.
end

Programming Note

The xscvqpswz instruction converts a quad-precision floating-point value to a signed word, rounding towards zero. It handles NaNs by setting the result to 0xFFFF_FFFF_8000_0000 and flags VXSNAN and VXCVI accordingly. For infinities, it sets the result to the maximum or minimum signed word value based on the sign of the infinity. Ensure that VSX is enabled (MSR.VSX=1) before using this instruction; otherwise, a VSX_Unavailable exception will be raised.

Example

xscvqpswz v1, v3

Encoding

Binary Layout
0
0
VRT
6
VRB
11
11
16
9
21
6
26
0
31
 
Format X-form
Opcode 0xFC090688
Extension VSX
Registers Altered FPSCR, VXSNAN, VXCVI, XX

Operands

  • VRT
    Target Vector-Scalar Register
  • VRB
    Source Vector-Scalar Register