bcdus.

Binary Coded Decimal Unsigned Shift

bcdus. VRT,VRA,VRB

Performs an unsigned shift on packed decimal values in vector registers.

Encoding

Binary Layout

Format VX-form

Opcode 0x10000481

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register containing the shift count
VRB
Source Vector Register containing the packed decimal value to be shifted

Example

bcdus. v1, v2, v3

Registers Altered

CR, XER

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The bcdus. instruction shifts the contents of VSR[VRB+32] by a number of digits specified by the signed integer value in byte element 7 of VSR[VRA+32]. The result is placed into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()

inv_flag ←0
do i = 0 to 31
    inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
end
eq_flag  ←(VSR[VRB+32].nibble[0:31] = 0)
gt_flag  ←(eq_flag=0)

if n > 0 then do     // shift left
    shcnt ←(n<33) ? n : 32
    src.nibble[0:31] ←VSR[VRB+32]
    src.nibble[32:63] ←0
    ox_flag ←(shcnt > 0) & (src.nibble[0:shcnt-1] != 0)
end else do              // shift right
    shcnt ←((¬n+1)<33) ? (¬n+1) : 32
    src.nibble[0:31] ←0
    src.nibble[32:63] ←VSR[VRB+32]
    result ←src.nibble[32-shcnt:63-shcnt]
    ox_flag ←0
end

VSR[VRT+32] ←inv_flag ? undefined : result

CR.bit[56] ←0b0
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

Programming Note

The bcdus. instruction is used for shifting Binary Coded Decimal (BCD) values within vector registers. Ensure that the shift count in byte element 7 of VSR[VRA+32] is valid; otherwise, the result is undefined. This instruction operates at the user privilege level and may raise an exception if vector processing is unavailable. Be cautious with alignment as it affects the interpretation of BCD digits.