vmhaddshs

Vector Multiply-High-Add Signed Halfword Saturate

vmhaddshs VRT,VRA,VRB,VRC

Performs a vector multiply-high-add signed halfword operation with saturation.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

VRC

21:25

26:31

Format VA-form

Opcode 0x10000020

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
VRC
Source Vector Register

Example

vmhaddshs v1, v2, v3, v4

Registers Altered

VSCR.SAT

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For each integer value i from 0 to 7, the signed integer value in halfword element i of VSR[VRA+32] is multiplied by the signed integer value in halfword element i of VSR[VRB+32], producing a 32-bit signed integer product. Bits 0:16 of the product are added to the signed integer value in halfword element i of VSR[VRC+32]. The low-order 16 bits of the result are placed into halfword element i of VSR[VRT+32]. If the intermediate result is greater than 2^15-1, the result saturates to 2^15 -1 and SAT is set to 1. If the intermediate result is less than -2^15, the result saturates to -2^15 and SAT is set to 1.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    src3 ←EXTS(VSR[VRC+32].hword[i])
    result ←((src1 × src2) >> 15) + src3
    VSR[VRT+32].hword[i] ←si16_CLAMP(result)
    VSCR.SAT ←sat_flag

Programming Note

This instruction is commonly used in applications requiring vectorized operations on signed halfwords, such as audio processing or graphics rendering. Ensure that the input vectors are properly aligned to avoid performance penalties. Be aware of saturation conditions; if any result exceeds the 16-bit signed integer range, it will be clamped and the VSCR.SAT flag will be set. This instruction operates at user privilege level.