stvxl

Store Vector Indexed Last

stvxl VS,RA,RB

Stores a vector element to memory, with the last element being stored if the index is out of bounds.

Encoding

Binary Layout

31

0:5

VS

6:10

RA

11:15

RB

16:20

487

21:30

/

31

 

Format X-form

Opcode 0x7C0003CE

Extension Base

Operands

• VS
  Vector Register
• RA
  Base Address General Purpose Register
• RB
  Index General Purpose Register

Example

stvxl vs1, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a vector from register VS to memory at the address formed by RA + RB. The address is aligned to the vector element size. This is a Base category instruction with no effect on condition or status registers.

Operation

EA ← (RA) + (RB)
MEM(EA, 16) ← VS

Programming Note

Use stvxl when storing vector data with a 'last touch' hint, potentially reducing cache line allocations. Ensure RA and RB are correctly set to form the aligned 16-byte address. This instruction is useful for optimizing memory usage in performance-critical sections.