vslq

Vector Shift Left Quadword

vslq vD, vA, vB

Shifts the contents of a vector register left by a specified number of bits.

Details

The vslq instruction shifts the contents of VSR[VRA+32] left by the number of bits specified in the low-order 7 bits of VSR[VRB+32]. The result is placed into VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()

let n be the contents of bits 57:63 of VSR[VRB+32]
let src1 be the contents of VSR[VRA+32]
let src2 be the contents of VSR[VRB+32]

src1 is shifted left by the number of bits specified in the low-order 7 bits of src2.

– Bits shifted out the most-significant bit are lost.
– Zeros are supplied to the vacated bits on the right.

The result is placed into VSR[VRT+32].

Programming Note

Ensure that the Vector Facility (MSR.VEC) is enabled before using vslq; otherwise, a Vector_Unavailable exception will occur. The shift amount is determined by the low-order 7 bits of the second source vector register, and shifts greater than 63 bits will result in zero being placed into the destination register.

Example

vslq vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
261
 
Format VX-form
Opcode 0x10000105
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Data
  • vB
    Shift
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Shift Count Vector Register