vslq

Vector Shift Left Quadword

vslq vD, vA, vB

Shifts the contents of a vector register left by a specified number of bits.

Details

Shifts the 128-bit contents of the source vector left by the number of bits specified in the shift-count register and stores the result in the destination vector. Bits shifted out the left end are discarded; zeros are shifted in from the right. The shift amount is taken modulo 128. No condition flags are affected; this is a VMX/AltiVec instruction.

Pseudocode Operation

shiftAmount ← vB[121:127] mod 128
vD[0:127] ← vA[0:127] << shiftAmount
vD[shiftAmount:127] ← 0 (shifted-in zeros)

Programming Note

Ensure that the Vector Facility (MSR.VEC) is enabled before using vslq; otherwise, a Vector_Unavailable exception will occur. The shift amount is determined by the low-order 7 bits of the second source vector register, and shifts greater than 63 bits will result in zero being placed into the destination register.

Example

vslq vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
261
 
Format VX-form
Opcode 0x10000105
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Data
  • vB
    Shift
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Shift Count Vector Register