xvf64gernn

VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form

xvf64gernn

Performs a VSX Vector 64-bit Floating-Point GER (rank-1 update) with negative multiply and negative accumulate, updating an accumulator register.

Details

The xvf64gernn instruction computes a rank-1 General External Product (GER) update using 64-bit floating-point values from two VSX vector registers. The products of corresponding elements are negated, and the result is subtracted from (negatively accumulated into) the target accumulator register. This instruction is part of the MMA (Matrix-Multiply Assist) facility introduced in PowerISA v3.1.

Pseudocode Operation

Not available in specification

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

xvf64gernn

Encoding

Binary Layout
59
0
AT
6
/
9
XA
11
XB
16
250
21
AX
29
BX
30
/
31
 
Format XX3-form
Opcode 0x7E000000
Extension MMA

Operands