xvf64gernn

VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form

xvf64gernn

Performs a VSX Vector 64-bit Floating-Point GER (rank-1 update) with negative multiply and negative accumulate, updating an accumulator register.

Details

Performs a VSX vector 64-bit floating-point outer-product update (GER rank-1 update) with negative multiply and negative accumulate. This MMA instruction is part of the Matrix Multiply Accumulate facility and requires MMA support; it reads two VSX vector registers and updates a 512-bit accumulator.

Pseudocode Operation

for i ∈ [0,1]:
  for j ∈ [0,1]:
    ACC[i,j] ← ACC[i,j] + (-(XA[i] * XB[j]))

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

xvf64gernn

Encoding

Binary Layout
59
0
AT
6
/
9
XA
11
XB
16
250
21
AX
29
BX
30
/
31
 
Format XX3-form
Opcode 0x7E000000
Extension MMA

Operands

  • AT
    Target 512-bit accumulator register to be updated with the product accumulation.
  • XA
    VSX vector source register providing the first operand (two 64-bit FP values).
  • XB
    VSX vector source register providing the second operand (two 64-bit FP values).