xvf64gernn

VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form

xvf64gernn AT,XAp,XB

Performs a VSX Vector 64-bit Floating-Point GER (rank-1 update) with negative multiply and negative accumulate, updating an accumulator register.

Encoding

Binary Layout
59
0:5
AT
6:8
/
9:10
XA
11:15
XB
16:20
250
21:28
AX
29
BX
30
/
31
 
Format XX3-form
Opcode 0xEC0007D0
Extension MMA

Operands

  • AT
    Target accumulator. ACC[AT] holds a 4x2 matrix of double-precision values.
  • XAp
    Source VSR pair (even/odd). VSR[XAp] and VSR[XAp+1] are concatenated to supply the four row values.
  • XB
    Source VSR supplying the two column values.

Example

xvf64gernn

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a VSX vector 64-bit floating-point outer-product update (GER rank-1 update) with negative multiply and negative accumulate. This MMA instruction is part of the Matrix Multiply Accumulate facility and requires MMA support; it reads two VSX vector registers and updates a 512-bit accumulator.

Operation

vsrcX ← VSR[XAp] || VSR[XAp+1]
vsrcY ← VSR[XB]
do i = 0 to 3
  do j = 0 to 1
    ACC[AT][i].dword[j] ← -( vsrcX.dword[i] × vsrcY.dword[j] + ACC[AT][i].dword[j] )
The product and the accumulated value are negated together.

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.