vmulouw

Vector Multiply Odd Unsigned Word

vmulouw vD, vA, vB

Multiplies the 1st and 3rd words of the source vectors to produce two 64-bit results.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

128

21:31

Format VA-form

Opcode 0x10000088

Extension VMX (AltiVec)

Operands

vD
Target
vA
Source A
vB
Source B

Example

vmulouw v1, v2, v3

// Widening multiply (32x32->64).

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the unsigned 32-bit words at positions 1 and 3 of vA by the corresponding words in vB, producing two unsigned 64-bit results stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.

Operation

vD[0:63] ← (vA[32:63] unsigned) × (vB[32:63] unsigned)
vD[64:127] ← (vA[96:127] unsigned) × (vB[96:127] unsigned)

Programming Note

This instruction is useful for performing element-wise multiplication of unsigned integers stored in odd-numbered positions of two vectors. Ensure that the input vectors are properly aligned to avoid alignment faults. The result is a vector with doubleword elements, so be mindful of potential overflow if the product exceeds 64 bits.