vmulouh

Vector Multiply Odd Unsigned Halfword

vmulouh vD, vA, vB

Multiplies odd unsigned halfwords to words.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

72

21:31

 

Format VX-form

Opcode 0x10000048

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vmulouh vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the odd-indexed unsigned halfwords from vA and vB, producing unsigned word results in vD. Operates on halfwords at indices 1 and 3, generating four word products without sign extension. No condition flags are affected.

Operation

vD[0:31] ← (vA[16:31] × vB[16:31]) as unsigned
vD[32:63] ← (vA[48:63] × vB[48:63]) as unsigned
vD[64:95] ← (vA[80:95] × vB[80:95]) as unsigned
vD[96:127] ← (vA[112:127] × vB[112:127]) as unsigned

Programming Note

This instruction is useful for performing element-wise multiplication of unsigned halfwords from two vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation targets odd-numbered halfwords, so developers should align their data accordingly to achieve the desired results.