xvminsp

VSX Vector Minimum Single-Precision

xvminsp XT, XA, XB

Performs a minimum operation on single-precision floating-point values from two vector scalar registers and stores the result in another vector scalar register.

Details

VSX Vector Minimum Single-Precision compares four single-precision floating-point elements from VSX registers XA and XB element-wise, selecting the minimum value for each element and storing results in VSX register XT. This VSX category instruction processes four 32-bit elements in parallel and follows IEEE 754 minimum semantics.

Pseudocode Operation

XT[0:31] ← min(XA[0:31], XB[0:31])
XT[32:63] ← min(XA[32:63], XB[32:63])
XT[64:95] ← min(XA[64:95], XB[64:95])
XT[96:127] ← min(XA[96:127], XB[96:127])

Programming Note

The xvminsp instruction is commonly used for performing element-wise minimum comparisons on single-precision floating-point values in VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be aware of the VXSNAN flag, which indicates a quiet NaN result; this can be checked via the FPSCR register. The instruction operates at the user privilege level and does not raise exceptions unless enabled through the FPSCR's VE (Invalid Operation Enable) bit.

Example

xvminsp vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
200
21
 
Format XX3-form
Opcode 0xF0000640
Extension VSX
Registers Altered FPSCR (FX, VXSNAN)

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B