stq

Store Quadword

stq RSp, DQ(RA)

Stores a quadword from two general-purpose registers into memory.

Encoding

Binary Layout
1
RSp
RA
DS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
 
Format DQ-form
Opcode 0xF8000002
Extension Base

Operands

  • RSp
    Src Pair
  • DQ
    Disp
  • RA
    Base
  • disp
    Displacement value

Example

stq r4, 0(r4)

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a 128-bit quadword from two consecutive general-purpose registers (RSp and RSp+1) into memory at the address formed by adding the base register (RA) and a 16-byte-aligned displacement. The displacement is a signed 12-bit value left-shifted by 4 bits, providing a range of ±2048 bytes on a 16-byte boundary. This instruction does not modify the condition register or status flags.

Operation

EA ← if RA = 0 then 0 else GPR[RA]
EA ← EA + EXTS(DQ || 0b0000)
MEM(EA, 16) ← GPR[RSp] || GPR[RSp+1]

Programming Note

In versions of the architecture prior to V. 2.07, this instruction was privileged.