vmaxsd

Vector Maximum Signed Doubleword

vmaxsd VRT,VRA,VRB

Compares the signed doublewords of two vector registers and stores the maximum value in a third vector register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:31

Format VX-form

Opcode 0x100001C2

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmaxsd v1, v2, v3

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmaxsd, each pair of corresponding doublewords from VSR[VRA+32] and VSR[VRB+32] are compared. The larger value is stored in the corresponding position in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ← VSR[VRA+32].dword[i]
    src2 ← VSR[VRB+32].dword[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].dword[i] ← gt_flag=1 ? src1 : src2
end

Programming Note

The vmaxsd instruction is used to perform element-wise maximum operations on signed doublewords from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation compares each pair of corresponding elements and stores the larger value in the destination register. This instruction operates at the user privilege level.