xvi8ger4pp

VSX Vector Integer 8-bit GER (Rank-4 Update) Plus/Plus

xvi8ger4pp AT, XA, XB

Signed/Unsigned variations of 8-bit matrix multiply accumulate.

Encoding

Binary Layout

60

0:5

AT

6:10

XA

11:15

XB

16:20

35

21:31

 

Format XX3-form

Opcode 0xEC000010

Extension MMA

Operands

• AT
  Accumulator
• XA
  Src A
• XB
  Src B

Example

xvi8ger4pp acc0, vs2, vs3

Registers Altered

ACC

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a rank-4 outer product accumulation of two 8-bit integer vectors, with sign/unsignedness controlled by inline suffix bits. The accumulate step uses saturating or wrapping semantics depending on configuration. This MMA instruction does not affect condition registers or status fields.

Operation

for i = 0 to 15 do
  for j = 0 to 15 do
    prod ← (int8)XA[8×i:8×i+7] × (int8)XB[8×j:8×j+7]
    ACC[AT][4×(i×16+j)] ← ACC[AT][4×(i×16+j)] + prod
  end for
end for

Programming Note

This instruction is commonly used in matrix operations where rank-4 updates are required. Ensure that the input vectors VSR[XA] and VSR[XB] are properly aligned to avoid performance penalties. The result is automatically chopped to fit into a 32-bit signed integer, so be cautious of overflow if intermediate results exceed this range.