lhzepx

Load Halfword and Zero External Process ID Indexed

lhzepx RT, RA, RB

Loads a halfword using the External PID.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

95

21:30

/

31

 

Format X-form

Opcode 0x7C0000BE

Extension Embedded

Operands

• RT
  Target
• RA
  Base
• RB
  Index

Example

lhzepx r3, r4, r5

Related

More in Embedded

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a halfword (16-bit value) from memory using an address formed by adding RA and RB, performing the load using the External PID for address translation in embedded environments. The loaded halfword is zero-extended and placed into RT. No condition flags are affected.

Operation

EA ← (RA) + (RB)
RT ← (64-48 bits are 0) || ([EA + 0:1])