sthci

Store Halfword Caching Inhibited

sthci RS, RA, RB

Stores a halfword bypassing the cache.

Details

The Store Halfword Caching Inhibited instruction stores a halfword bypassing the cache.

Pseudocode Operation

Memory[address] <- r3

Example

sthci r3, r4, r5

Encoding

Binary Layout

31

0

RS

6

RA

11

RB

16

1014

21

/

31

Format X-form

Opcode 0x7C0007EE

Extension Base

Operands

RS
Source
RA
Base
RB
Index