sthci

Store Halfword Caching Inhibited

sthci RS, RA, RB

Stores a halfword bypassing the cache.

Details

Store a halfword from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The halfword is written directly to L2 or memory depending on cache hierarchy. This instruction requires cache-inhibited access and is typically used for memory-mapped I/O or special memory regions.

Pseudocode Operation

addr ← (RA) + (RB)
[(addr)] ← (RS)[48:63]
Memory write with cache inhibit attribute

Example

sthci r3, r4, r5

Encoding

Binary Layout
31
0
RS
6
RA
11
RB
16
1014
21
/
31
 
Format X-form
Opcode 0x7C0007EE
Extension Base

Operands

  • RS
    Source
  • RA
    Base
  • RB
    Index