sthci

Store Halfword Caching Inhibited

sthci RS, RA, RB

Stores a halfword bypassing the cache.

Encoding

Binary Layout

31

0:5

RS

6:10

RA

11:15

RB

16:20

1014

21:30

/

31

 

Format X-form

Opcode 0x7C0007EE

Extension Base

Operands

• RS
  Source
• RA
  Base
• RB
  Index

Example

sthci r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Store a halfword from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The halfword is written directly to L2 or memory depending on cache hierarchy. This instruction requires cache-inhibited access and is typically used for memory-mapped I/O or special memory regions.

Operation

addr ← (RA) + (RB)
[(addr)] ← (RS)[48:63]
Memory write with cache inhibit attribute