xsredp

Vector Scalar Reciprocal Estimate Double Precision

xsredp XT,XB

Estimates the reciprocal of a double-precision floating-point value.

Details

The xsredp instruction estimates the reciprocal of a double-precision floating-point value in VSR[XB].dword[0] and places the result into VSR[XT].dword[0]. The contents of VSR[XT].dword[1] are set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[XB+32].dword[0])
v ← bfp_RECIPROCAL_ESTIMATE(src)
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if zx_flag=1 then SetFX(FPSCR.ZX)
vex_flag ← FPSCR.VE & vxsnan_flag
zex_flag ← FPSCR.ZE & zx_flag
if vex_flag=0 & zex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
    FPSCR.FI ← 0bU
VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FR ← 0bU

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xsredp vs1, vs3

Encoding

Binary Layout
18
0
T
6
B
11
90
16
 
Format XX2-form
Opcode 0xF0000168
Extension VSX
Registers Altered FPSCR.FR, FPSCR.FPRF, FPSCR.FI, FPSCR.VXSNAN, FPSCR.OX, FPSCR.UX, FPSCR.ZX

Operands

  • XT
    Target Vector-Specific Register
  • XB
    Source Vector-Specific Register
  • %xT
    Target Vector Register
  • %xS
    Source Vector Register