vdivsw

Vector Divide Signed Word

vdivsw VRT,VRA,VRB

Divides the contents of two vector registers and updates the result in another vector register.

Encoding

Binary Layout

4

0:5

VRT

6:10

VRA

11:15

VRB

16:31

 

Format VX-form

Opcode 0x1000018B

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vdivsw v1, v2, v3

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vdivsw, each word element of VSR[VRA+32] is divided by the corresponding word element of VSR[VRB+32]. The quotient is placed into the corresponding word element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    dividend ←EXTS(VSR[VRA+32].word[i])
    divisor  ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(dividend ÷ divisor)
end

Programming Note

vdivsw performs element-wise signed word division. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. Handle potential division by zero and overflow conditions in your application logic.