vsubuwm

Vector Subtract Unsigned Word Modulo

vsubuwm vD, vA, vB

Subtracts the contents of two vector registers and updates the result in another vector register.

Details

For vsubuwm, each word element in VSR[VRB+32] is subtracted from the corresponding word element in VSR[VRA+32]. The low-order 32 bits of the result are placed into the corresponding word element in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(src1 + ¬src2 + 1)
end

Programming Note

This instruction performs unsigned word modulo subtraction on vector registers. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow conditions, as this operation does not handle carry-out explicitly. The operation is performed on 32-bit words, so ensure proper alignment if dealing with larger data types.

Example

vsubuwm v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
1152
21
 
Format VA-form
Opcode 0x10000480
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Source A
  • vB
    Source B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register