divdeu

Divide Doubleword Extended Unsigned

divdeu RT, RA, RB

64-bit extended unsigned division.

Details

The divdeu instruction performs an unsigned division of a 64-bit dividend by a 64-bit divisor. The quotient is placed into the target register RT, and the remainder is not supplied as a result. Both operands and the quotient are interpreted as unsigned integers.

Pseudocode Operation

dividend0:63 ←(RA)
divisor0:63 ←(RB)
RT ← dividend ÷ divisor

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divdeu r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
OE
21
393
22
Rc
31
 
Format XO-form
Opcode 0x7C000312
Extension Base
Registers Altered CR0

Operands

  • RT
    Target
  • RA
    Dividend
  • RB
    Divisor