divdeu

Divide Doubleword Extended Unsigned

divdeu RT, RA, RB

64-bit extended unsigned division.

Details

Performs unsigned extended division of a 128-bit dividend (RA || R0) by the 64-bit unsigned divisor in RB, placing the 64-bit quotient in RT. If OE=1 and overflow occurs, the OV bit in XER is set; if Rc=1, CR0 is set based on the quotient. Division by zero produces undefined results.

Pseudocode Operation

dividend ← (RA || 0)  # 128-bit value: RA in high 64 bits, 0 in low 64 bits
RT ← dividend / RB
if OE = 1 then
  XER[OV] ← overflow_flag
if Rc = 1 then
  CR0 ← (RT_comparison_summary)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divdeu r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
OE
21
393
22
Rc
31
 
Format XO-form
Opcode 0x7C000312
Extension Base
Registers Altered CR0

Operands

  • RT
    Target
  • RA
    Dividend
  • RB
    Divisor