divsq

Divide Signed Quadword

divsq vD, vA, vB

Divides a 128-bit signed integer by a 128-bit signed integer (using VSX pairs).

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

265

21:31

 

Format VX-form

Opcode 0x10000109

Extension Base

Operands

• vD
  Target
• vA
  Dividend
• vB
  Divisor

Example

divsq vd, va, vb

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Divides a 128-bit signed integer dividend (vA) by a 128-bit signed integer divisor (vB) and stores the 128-bit signed quotient in vD. This instruction operates on VSX vector register pairs and is part of the Base category with extended integer support. Division by zero results in undefined behavior; no overflow exception is generated.

Operation

vD ← (vA) /s (vB)