vdivesd

Vector Divide Extended Signed Doubleword

vdivesd VRT,VRA,VRB

Performs extended signed doubleword division on vector elements.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:31

Format VX-form

Opcode 0x100003CB

Extension VMX (AltiVec)

Operands

VRT
Destination Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vdivesd v1, v2, v3

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vdivesd, each element of the source vectors VRA and VRB is treated as a signed doubleword. The dividend is shifted left by 64 bits, then divided by the divisor. The quotient is placed into the corresponding element of the destination vector VRT.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    dividend ←EXTS(VSR[VRA+32].dword[i]) << 64
    divisor  ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(dividend ÷ divisor)
end

Programming Note

This instruction is used for performing extended signed doubleword division on vector elements. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation involves shifting each dividend left by 64 bits and then dividing it by the corresponding divisor, with the quotient being stored in the destination vector. Be cautious of potential division by zero errors, which may result in undefined behavior or exceptions.