vprtybq

Vector Parity Byte Quadword

vprtybq vD, vB

Calculates the parity of each byte in a vector register and stores the result in another vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1668

21:31

Format VX-form

Opcode 0x100A0602

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source
VRT
Target Vector Register
VRB
Source Vector Register

Example

vprtybq vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Computes the parity bit for each byte in the 128-bit source vector and stores the result in the destination vector. The parity of each byte is XORed across all 8 bits, producing a single bit (0 or 1) for each byte. This is a VMX/AltiVec extension instruction and does not affect condition registers or status fields.

Operation

for i in 0 to 15 do
  parity_bit ← 0
  for j in 0 to 7 do
    parity_bit ← parity_bit XOR vB[i*8 + j]
  vD[i*8:i*8+7] ← (0b0000000 || parity_bit)
end

Programming Note

The vprtybq instruction calculates the parity of each byte in the source vector register VRB and stores the result in the target vector register VRT. Ensure that the Vector Facility is enabled by checking and setting the MSR.VEC bit. The instruction processes 16 bytes from VRB, and the result is a single bit indicating the parity for each byte, which is then replicated across all 128 bits of VRT.