vsubuws

Vector Subtract Unsigned Word Saturate

vsubuws vD, vA, vB

Subtracts the contents of two vector registers and saturates the result if it underflows.

Details

For vsubuws, each word element in VSR[VRB+32] is subtracted from the corresponding word element in VSR[VRA+32]. If the intermediate result is less than 0, it saturates to 0 and sets the SAT field in VSCR.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←ui32_CLAMP(src1 + ¬src2 + 1)
end

Programming Note

This instruction is commonly used for vectorized unsigned word subtraction with saturation, useful in image processing and other applications requiring bounded arithmetic. Ensure that the Vector Status and Control Register (VSCR) is properly managed to handle saturation flags. The operation saturates underflows to zero, so be cautious of cases where results might wrap around unexpectedly.

Example

vsubuws vd, va, vb

Encoding

Binary Layout
4
4
vD
6
vA
11
vB
16
1664
 
Format VX-form
Opcode 0x10000680
Extension VMX (AltiVec)
Registers Altered VSCR.SAT

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register