mfsr

Move From Segment Register

mfsr RT, SR

Legacy 32-bit segment register read.

Encoding

Binary Layout

31

0:5

RT

6:10

SR

11:15

/

16:20

595

21:30

/

31

 

Format X-form

Opcode 0x7C0004A6

Extension Base

Operands

• RT
  Target
• SR
  Segment Reg

Example

mfsr r3, 0

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Reads a 32-bit Segment Register (legacy 32-bit PowerPC mode) and stores the value in RT. This instruction is used only in 32-bit addressing mode and is deprecated in 64-bit architecture. No condition or status registers are modified.

Operation

RT ← SR[SR number from instruction]