xsmaddadp
VSX Scalar Multiply-Add Type-A Double-Precision
Performs a double-precision floating-point multiply-add operation.
Details
For xsmaddadp, do the following. Let src1 be the double-precision floating-point value in doubleword element 0 of VSR[XA]. Let src2 be the double-precision floating-point value in doubleword element 0 of VSR[XT]. Let src3 be the double-precision floating-point value in doubleword element 0 of VSR[XB].
Pseudocode Operation
if 'xsmaddadp' then do
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ←bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
FPSCR.FPRF ←fprf_CLASS_BFP64(result)
FPSCR.FR ←inc_flag
FPSCR.FI ←xx_flag
end else do
FPSCR.FR ←0b0
FPSCR.FI ←0b0
end
end
Programming Note
This instruction performs a scalar multiply-add operation on double-precision floating-point values. Ensure that the VSX registers are properly aligned and initialized before use. The result is rounded according to the rounding mode specified in the FPSCR register. Be aware of potential exceptions such as NaNs, infinities, or underflows, which can set flags in the FPSCR.
Example
Encoding
Operands
-
XT
Target Vector-Specific Register -
XA
Source Vector-Specific Register -
XB
Source Vector-Specific Register